The decoding and display of standard-definition video signals requires a reference clock with a frequency that is an integral multiple of 27 Mhz and the decoding and display of high-definition video signals requires a reference clock with a frequency of 148.35164 MHz, which is not an integral multiple of 27 MHz. Furthermore, some other high-definition video signals require a reference clock with a frequency of 148.5 MHz, which is also not an integral multiple of 27 MHz. The techniques for generating these three reference clocks simultaneously from the same reference crystal clock source in the prior art all have disadvantages, and, therefore, the need exists for a more elegant solution for doing so.